Programmable integrated circuits generally are known to lend circuit designers flexibility in the design of electrical circuits. Before the advent of programmable integrated circuits, previous technologies often required board-level implementation of circuit designs, wherein various chips of fixed logic gates would be interconnected with fixed wiring configurations. If warranted, a custom integrated circuit might then be developed to further evolve the board solution into a custom integrated circuit of higher-density and smaller size. But as was often the case, an inadvertent error in the initial circuit design, tape-out and/or mask generation for the custom integrated circuit or perhaps even a simple change in the design criteria would force a costly fix, re-engineering or repeat design cycle.
With the development of programmable integrated circuits such as Programmable Logic Devices (PLDs), the process of digital or even analog hardware design has changed dramatically. Various devices such as processors, memory, logic circuits for state machine controllers, counters, registers, decoders and comparators may now be more readily realized for various configurations and even re-worked within prototypes or low-volume applications, as known, by assistance of programmable integrated circuit devices such as the PLDs. The Programmable Logic Devices may thus be understood to offer benefits of substantially instantaneous turnarounds, reduced costs, reduced risks and ease in engineering.
A typical PLD may include a plurality of programmable resources such as an AND plane and an OR plane of known Programmable Array Logic (PAL) type structure. The logic plane(s) may be programmable via known configuration memory as allocated to particular wiring-links for the plane for enabling the programmable resources to be configurable to various user defined functions. In some cases, flip-flops may also be connected or configurable for connection to the outputs of the OR-gate outputs so that sequential circuits can be further realized. The device may also include bi-direction I/Os around the periphery. These I/Os in turn may be connected to Generic Logic Blocks (as a form of small PAL) and/or also the Global Routing Pool(s). Such variations for the PAL type architecture may further be understood by some artisans to be incorporated with such PLDs.
Standard PLDs are known to include configuration memory operable to receive and store configuration data by which to configure the programmable resources of the PLD as allocated thereto. In the case of non-volatile type configuration memory for PLDs, the memory may comprise electrically erasable programmable non-volatile memory (i.e., EEPROM or E2 cells) as known. Accordingly, the PLD may be purchased by system designers or manufactures in a “blank” state and then configured as desired by the user into virtually an unlimited number of specific functions. Being electrically erasable, the system designers may then be able to quickly create modifications to the initial custom logic function without having to endure great sacrifice in a project timeline.
It may be further recognized that manufactures of PLDs seem to continually push for realizations of smaller size and ever increasing density, presumably for enhancing manufacturing cost efficiencies. Such density increases and geometry reductions may in turn be found to place a greater premium on testing. As the densities increase for PLDs, the test processes and associated test times may be understood to contribute toward a greater portion of the overall costs in the production of the devices. To verify operability of the configurable resources of the PLD, each of the various possible configurations for the configurable logic blocks and various interconnect structures may need to be implemented which in turn may be understood to require a significant amount of time for erasing and reprogramming of the E2 cells. For some PLDs, this erase and reprogram overhead for testing may accrue to as much as one third of an overall cost therefore, more especially so as their die size decreases.
For some known PLDs, volatile bits may be formed on the device (essentially as redundant bits) to be effective and operable to “mirror” each of the non-volatile programmable bits. During test, the redundant mirror bits may be employed to set the configurations of the PLD during test. However, while the added expense for these mirror bits to assist testing of the PLD may not be particularly bothersome for large scale integrated circuits, the real estate overhead may become more significant for small size PLDs. Further, the additional latches or registers constituting the source for the test date configuration may be understood as more of an alternative avenue by which to configure the programmable resources. Thus, this approach may essentially by-pass the data path from the configuration memory to the configurable resources, and may be found to not “truly mirror” the configuration memory for enabling testing of data paths from the configuration memory cells to the respective configurable programmable resources. In other words, the programmable interconnect between the actual E2 cells and their destination may not be effectively tested and verified.